1. Field of the Invention
This invention relates to DLLs, and more particularly, to a DLL with automatic reset functionality.
2. Description of the Prior Art
Delay Locked Loops (DLLs) are devices comprising a variable delay line in a first-order feedback loop that lock an output phase with an input reference signal. A typical application of DLLs is in DRAMs, where they are used to synchronize the DRAM data output strobe (DQS) and data (DQ) with the external clock input (VCLK).
When the DLL is in a lock state, the rising edge of the data strobe will align with the rising edge of the external clock. This behavior should remain stable over a defined clock frequency of the system.
When the external clock frequency changes after the DLL is locked, the DLL must track and re-lock to the new phase. Although most systems issue DLL reset each time the clock frequency changes according to the JEDEC specification, this does not occur in every system, and the DLL will therefore have to re-sync to the correct edge from the original sync position. If the phase shift is small, the DLL will be able to perform this operation relatively quickly, but if the phase shift is great, the DLL will take a long time to re-sync.